Summary

A solid foundation in design and optimization of on-chip caches, DRAMs and Disk drives (both mechanical and SSDs). I focus on new technologies and most of my readings are from significant papers in the industry. A strong understanding at the graduate school level, and continual refresh of my knowledge at the industry level has really made this topic my forte. In-depth understanding of NAND and NOR flash, NAND-toDRAM controllers, spinnning hard drive design, and emerging technologies - ReRAM and other phase-change memories.

Expert in memory timing analysis, FTL (Flash Translation Layer) code development and architecture, including Garbage Collection algorithms, optimizations for power and performance, and low-level comand validation.

Implementation and debug of power saving techniques for on-chip caches, namely Gated-VDD and Drowsy cache design. Both were coded up using the SESC MIPS simulator. In addition to the implementation, evaluated both designs for performance across industry benchmarks from SPEC and SPLASH2.

Tools

• Programming in C and C++
• Test automation using Python
• Timing and Command Validation using Logic Analyzers